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FUJITSU SEMICONDUCTOR DATA SHEET
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DS07-05604-1E
MB86943B
s DESCRIPTION
The MB86943B is a bus bridge that allows high-speed [data] transfers between the host processor (SPARClite* Family) and the PCI-bus. This bridge chip enables SPARClite (host CPU) access in program mode (direct master operation) to devices on a PCI bus. Also, the SPARClite host can invoke the built-in DMA function on the bridge chip to allow access to devices on the PCI bus. Access from the PCI side to devices on the SPARClite bus (SL bus) is enabled by using the bridge chip slave operation function. The DMA function can be started up from the SL-bus side. The MB86943B supports Door Bell functions and Mail Box function as well. * : SPARClite is a trademark of SPARC International, Inc. in the United States. Fujitsu Microelectronics, Inc. has been granted permission to use the trademark.
s FEATURES
Key hardware features * Functions for SL-bus to PCI slave (possible to work in program mode) * Functions for PCI-bus to SL-bus slave (possible to work in program mode) * Two-channel DMA functions (between the SL-bus and the PCI-bus) * Functions to access the SL-bus's external areas (ECS0 through ECS2) * Interrupt communication functions between the SL-bus and the PCI-bus by use of Door Bell and Mail Box.
s PACKAGE
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(Continued)
352-pin Plastic BGA
(BGA-352P-M03)
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MB86943B
(Continued)
Bus bridge features The host SPARClite can access the PCI-bus's target by use of the chip's PCI-bus direct master functions (Direct Master Operation). Also the PCI-bus's other masters can access the SPARClite bus by use of the chip's PCIbus direct slave functions (Direct Slave Operation). These functions allow individual bus masters to mutually access the PCI-bus area and SL-bus area. With the Direct Master or the Direct Slave in operation, data are transferred via the 128-byte data buffer, so that a high-speed burst transfer can be achieved. * Direct Master Operation Allows the SL-bus processor to directly access the PCI space. Allows high-speed burst transfer via the relevant data buffer. * Direct Slave Operation Allows the PCI-bus master to directly access the SL-bus space. Allows high-speed burst transfer via the relevant data buffer. Provided with two independent DMA channels * Carries out 32/64-bit transfer. * Possible to work DMA control from the SL-bus side. * Bidirectional DMA functions by use of the bidirectional data buffer having a capacity of 128 bytes. * High-speed data chain mode by use of the built-in registers. High Speed Data Chain Mode Using Internal Registers. Because DMA descriptors are stored in internal registers there is no need to fetch descriptors from external memory, enabling high speed DMA operations in descriptor chain mode. Functions to access the SL-bus's external areas * Pins ECS0 through ECS2 (External Chip Select) allow the access to the SL-bus's external I/Os, the memory via the bridge chip. Door Bell functions The functions notify bidirectional interrupts; SL-bus PCI-bus and PCI-bus SL-bus. Mail Box functions Provided with eight registers possible to perform PCI write/SL read and eight registers possible to perform SL write/PCI read, so that messages can be communicated from both sides. A means is also provided to interrupt from the writing side to the reading side at same time. The PCI-bus and the SL-bus can operate asynchronously by use of different clocks. Data bus widths SL-bus PCI-bus 64/32 bits. 64/32 bits.
Address bus widths SL-bus PCI-bus 32 bits (fixed) ADR<1:0> ignored, ASI<3:0> supported. 64/32 bits.
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MB86943B
s PIN ASSIGNMENT
INDEX A B C D E F GH J K L MN P R T U V W Y AA AB AC AD AE AF
1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 2 100101102103104105106107108109110111112113114115116117118119120121122123124 27 3 99 192193194195196197198199200201202203204205206207208209210211212213214125 28 4 98 191276277278279280281282283284285286287288289290291292293294295296215126 29 5 97 190275352 297216127 30 6 96 189274351 298217128 31 7 95 188273350 299218129 32 8 94 187272349 300219130 33 9 93 186271348 301220131 34 10 92 185270347 302221132 35 11 91 184269346 303222133 36 12 90 183268345 304223134 37 13 89 182267344 (BOTTOM-VIEW) 305224135 38 14 88 181266343 306225136 39 15 87 180265342 307226137 40 16 86 179264341 308227138 41 17 85 178263340 303228139 42 18 84 177262339 310229140 43 19 83 176261338 311230141 44 20 82 175260337 312231142 45 21 81 174259336 313232143 46 22 80 173258335 314233144 47 23 79 172257334333332331330329328327326325324323322321320319318317316315234145 48 24 78 171256255254253252251250249248247246245244243242241240239238237236235146 49 25 77 170169168167166165164163162161160159158157156155154153152151150149148147 50 26 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
Signals (259 pins); 248 pins of them already used 282, 301, 320, 339, 196, 108, 20, 23 VDD3 (32 pins) Iinternal LOGIC, 287, 306, 325, 344, 299, 131, 45, 48 Power-supply for I/Os 291, 310, 329, 348, 54, 154, 70, 73 296, 315, 334, 277 79, 177, 270, 98 VDD5 (21 pins) 281, 300, 319, 338, 194, 198, 112, 15, 209, 212 Power-supply for PCI 286, 305, 324, 343, 215, 272, 275 I/Os 292, 311, 330, 349 VSS (38 pins) 1, 26, 51, 76, 195, 6, 285, 288, 210, 121 Iinternal LOGIC, 279, 298, 317, 336, 216, 129, 39, 312 GND common to I/Os 284, 303, 322, 341, 55, 64, 331, 289, 308, 327, 346, 80, 89, 186, 273, 190 294, 313, 332, 351 VPDP (1 pin) 92 When mounted, connected to VSS A feed-through current prevention cell OVSENS (1 pin) 93 When mounted, connected to VSS A power-sensing cell
3
MB86943B
PKG Pin number FJ 1 279 282 2 101 103 102 3 194 195 278 4 104 105 196 5 280 106 197 198 6 107 7 199 108 200 8 283 9 281 JEDEC A1 F4 J4 B1 B2 D2 C2 C1 D3 E3 E4 D1 E2 F2 F3 E1 G4 G2 G3 H3 F1 H2 G1 J3 J2 K3 H1 K4 J1 H4
Pin name VSS VSS VDD3 AD[19] AD[18] FRAME# AD[17] C/BE[2]# VDD5 VSS TRDY# IRDY# (N.C.) STOP# VDD3 AD[15] SERR# PAR VDD5 VSS AD[12] PERR# AD[13] VDD3 AD[11] C/BE[1]# AD[09] AD[14] VDD5
Attribute VSS VSS VDD3 PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O VDD5 VSS PCI I/O PCI I/O N.C. PCI I/O VDD3 PCI I/O PCI I/O PCI I/O VDD5 VSS PCI I/O PCI I/O PCI I/O VDD3 PCI I/O PCI I/O PCI I/O PCI I/O VDD5
PKG Pin number FJ 284 109 10 201 110 202 11 287 12 285 112 111 13 203 14 204 113 114 15 288 16 291 115 205 17 206 18 116 289 JEDEC L4 K2 K1 L3 L2 M3 L1 P4 M1 M4 N2 M2 N1 N3 P1 P3 P2 R2 R1 R4 T1 V4 T2 R3 U1 T3 V1 U2 T4
AtPin name tribute VSS AD[08] AD[10] C/BE[0]# AD[04] AD[06] AD[07] VDD3 AD[05] VSS VDD5 AD[00] AD[03] AD[02] AD[01] REQ64# ACK64# C/BE[6]# VDD5 VSS C/BE[4]# VDD3 PAR64 C/BE[7]# AD[63] C/BE[5]# AD[59] AD[61] VSS VSS PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O VDD3 PCI I/O VSS VDD5 PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O VDD5 VSS PCI I/O VDD3 PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O VSS
PKG Pin number FJ 286 19 290 117 207 20 208 21 118 210 209 22 119 293 120 211 23 121 212 24 295 213 122 123 25 214 292 294 296 JEDEC N4 W1 U4 V2 U3 Y1 V3 AA1 W2 Y3 W3 AB1 Y2 Y4 AA2 AA3 AC1 AB2 AB3 AD1 AB4 AC3 AC2 AD2 AE1 AD3 W4 AA4 AC4
Pin name VDD5
Attribute VDD5
AD[57] PCI I/O AD[60] PCI I/O AD[56] PCI I/O AD[62] PCI I/O VDD3 VDD3 AD[58] PCI I/O AD[53] PCI I/O AD[54] PCI I/O VSS VDD5 VSS VDD5
AD[51] PCI I/O AD[55] PCI I/O AD[52] PCI I/O AD[49] PCI I/O AD[50] PCI I/O VDD3 VSS VDD5 VDD3 VSS VDD5
DEVSEL# PCI I/O
AD[45] PCI I/O AD[48] PCI I/O AD[46] PCI I/O AD[47] PCI I/O AD[42] PCI I/O AD[43] PCI I/O AD[44] PCI I/O VDD5 VSS VDD3 VDD5 VSS VDD3
VDD3 : A 3.3 V power-supply pin (for supplying I/O power and internal power) VDD5 : Either a 5 V power-supply pin or 3.3 V power-supply pin (for supplying power to PCI I/Os) N.C. : Use this in an open state.
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MB86943B
PKG Pin number FJ 26 298 301 27 124 126 125 28 215 216 297 29 127 128 217 30 299 129 218 219 31 130 32 220 131 221 33 302 34 300 JEDEC AF1 AC6 AC9 AF2 AE2 AE4 AE3 AF3 AD4 AD5 AC5 AF4 AE5 AE6 AD6 AF5 AC7 AE7 AD7 AD8 AF6 AE8 AF7 AD9 AE9 AD10 AF8 AC10 AF9 AC8
Pin name VSS VSS VDD3 AD[41] AD[40] AD[36] AD[38] AD[39] VDD5 VSS AD[34] AD[37] AD[33] AD[35] AD[32] (N.C.) VDD3 VSS EAS# ECS0# ECS1# ECS2# EBMREQ# EBMACK# VDD3 DRQ0# DACK0# EOP0# DRQ1# VDD5
Attribute VSS VSS VDD3 PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O VDD5 VSS PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O N.C. VDD3 VSS O O O O O I* VDD3 I* O O I* VDD5
PKG Pin number FJ 303 132 35 222 133 223 36 306 37 304 135 134 38 224 39 225 136 137 40 307 41 310 138 226 42 227 43 139 308 JEDEC AC11 AE10 AF10 AD11 AE11 AD12 AF11 AC14 AF12 AC12 AE13 AE12 AF13 AD13 AF14 AD14 AE14 AE15 AF15 AC15 AF16 AC18 AE16 AD15 AF17 AD16 AF18 AE17 AC16
Pin name VSS DACK1# EOP1# (N.C.) ADR<2> ADR<3> ADR<4> VDD3 ADR<5> ADR<6> ADR<7> ADR<8> ADR<9> ADR<10> VSS ADR<11> ADR<12> ADR<13> ADR<14> ADR<15> ADR<16> VDD3 ADR<17> ADR<18> ADR<19> ADR<20> ADR<21> ADR<22> VSS
Attribute VSS O O N.C. I/O* I/O* I/O* VDD3 I/O* I/O* I/O* I/O* I/O* I/O* VSS I/O* I/O* I/O* I/O* I/O* I/O* VDD3 I/O* I/O* I/O* I/O* I/O* I/O* VSS
PKG Pin number FJ 305 44 309 140 228 45 229 46 141 231 230 47 142 312 143 232 48 144 233 49 314 234 145 146 50 235 311 313 315 JEDEC AC13 AF19 AC17 AE18 AD17 AF20 AD18 AF21 AE19 AD20 AD19 AF22 AE20 AC20 AE21 AD21 AF23 AE22 AD22 AF24 AC22 AD23 AE23 AE24 AF25 AD24 AC19 AC21 AC23
Pin name VDD5 ADR<23> ADR<24> ADR<25> ADR<26> VDD3 ADR<27> ADR<28> ADR<29> ADR<30> ADR<31> (N.C.) BMREQ# VSS BMACK# ERROR# VDD3 RGSL# BMINH# WINDOWS# ASI<0> ASI<1> ASI<2> ASI<3> SRSTO# SRSTI# VDD5 VSS VDD3
Attribute VDD5 I/O* I/O* I/O* I/O* VDD3 I/O* I/O* I/O* I/O* I/O* N.C. I/O* VSS I/O* I* VDD3 I* I* I* I* I* I* I* t/s O I* VDD5 VSS VDD3
* : With a pull-up resistor VDD3 : A 3.3 V power-supply pin (for supplying I/O power and internal power) VDD5 : Either a 5 V power-supply pin or 3.3 V power-supply pin (for supplying power to PCI I/Os) N.C. : Use this in an open state.
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MB86943B
PKG Pin number FJ 51 317 320 52 147 149 148 53 236 237 316 54 150 151 238 55 318 152 239 240 56 153 57 241 154 242 58 321 59 319 JEDEC AF26 AA23 V23 AE26 AE25 AC25 AD25 AD26 AC24 AB24 AB23 AC26 AB25 AA25 AA24 AB26 Y23 Y25 Y24 W24 AA26 W25 Y26 V24 V25 U24 W26 U23 V26 W23
Pin name VSS VSS VDD3 CLKIN TMS TRST# TCK TDO TDI BREQ# BGRNT# VDD3 BRIN# BGOUT# PBREQ# VSS BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# VDD3 (N.C.) RDWR# AS# (N.C.) VDD5
Attribute VSS VSS VDD3 I I* I* I* O I* O I* VDD3 I* O I* VSS I/O
PKG Pin number FJ 322 155 60 243 156 244 61 325 62 323 158 157 63 245 64 246 159 160 65 326 66 329 161 247 67 248 68 162 327 JEDEC T23 U25 U26 T24 T25 R24 T26 N23 R26 R23 P25 R25 P26 P24 N26 N24 N25 M25 M26 M23 L26 J23 L25 M24 K26 L24 J26 K25 L23
Pin name VSS D<0> D<1> D<2> D<3> D<4> D<5> VDD3 D<6> D<7> DP7 D<8> D<9> D<10> VSS D<11> D<12> D<13> D<14> D<15> DP6 VDD3 D<16> D<17> D<18> D<19> D<20> D<21> VSS
PKG Pin number Attribute FJ JEDEC VSS I/O* I/O* I/O* I/O* I/O* I/O* VDD3 I/O* I/O* I/O* I/O* I/O* I/O* VSS I/O* I/O* I/O* I/O* I/O* I/O* VDD3 I/O* I/O* I/O* I/O* I/O* I/O* VSS 324 69 328 163 249 70 250 71 164 252 251 72 165 331 166 253 73 167 254 74 333 255 168 169 75 256 330 332 334 P23 H26 K23 J25 K24 G26 J24 F26 H25 G24 H24 E26 G25 G23 F25 F24 D26 E25 E24 C26 E23 D24 D25 C25 B26 C24 H23 F23 D23
Pin name VDD5 D<22> D<23> DP5 D<24> VDD3 D<25> D<26> D<27> D<28> D<29> D<30> D<31> VSS DP4 D<32> VDD3 D<33> D<34> D<35> D<36> D<37> D<38> D<39> DP3 D<40> VDD5 VSS VDD3
Attribute VDD5 I/O* I/O* I/O* I/O* VDD3 I/O* I/O* I/O* I/O* I/O* I/O* I/O* VSS I/O* I/O* VDD3 I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* VDD5 VSS VDD3
I/O* I/O* I/O* I/O* I/O* I/O* I/O* VDD3 N.C. I/O* I/O* N.C. VDD5
* : With a pull-up resistor VDD3 : A 3.3 V power-supply pin (for supplying I/O power and internal power) VDD5 : Either a 5 V power-supply pin or 3.3 V power-supply pin (for supplying power to PCI I/Os) N.C. : Use this in an open state.
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MB86943B
PKG Pin number FJ 76 336 339 77 170 172 171 78 257 258 335 79 173 174 259 80 337 175 260 261 81 176 82 262 177 263 83 340 84 338 JEDEC A26 D21 D18 A25 B25 B23 B24 A24 C23 C22 D22 A23 B22 B21 C21 A22 D20 B20 C20 C19 A21 B19 A20 C18 B18 C17 A19 D17 A18 D19
Pin name VSS VSS VDD3 D<41> D<42> D<43> D<44> D<45> D<46> D<47> DP2 VDD3 D<48> D<49> D<50> VSS D<51> D<52> D<53> D<54> D<55> DP1 D<56> D<57> VDD3 D<58> D<59> D<60> D<61> VDD5
Attribute VSS VSS VDD3 I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* VDD3 I/O* I/O* I/O* VSS I/O* I/O* I/O* I/O* I/O* I/O* I/O* I/O* VDD3 I/O* I/O* I/O* I/O* VDD5
PKG Pin number FJ 341 178 85 264 179 265 86 344 87 342 181 180 88 266 89 267 182 183 90 345 91 348 184 268 92 269 93 185 346 JEDEC D16 B17 A17 C16 B16 C15 A16 D13 A15 D15 B14 B15 A14 C14 A13 C13 B13 B12 A12 D12 A11 D9 B11 C12 A10 C11 A9 B10 D11
Pin name VSS D<62> D<63> DP0 (N.C.) READY# READYIN# VDD3 RDYOUT# MEXC# IRQ# (N.C.) HOST SLD64 VSS BST8 (N.C.) TEST0 TEST1 TEST2 TEST3 VDD3 (N.C.) (N.C.) VPDP INTA# OVSENSE CLK VSS
Attribute VSS I/O* I/O* I/O* N.C. t/s O I VDD3 I t/s O O N.C. I* I* VSS I* N.C. O O O O VDD3 N.C. N.C. VPDP PCI O PCI I VSS
PKG Pin number FJ 343 94 347 186 270 95 271 96 187 273 272 97 188 350 189 274 98 190 275 99 352 276 191 192 100 193 351 277 JEDEC D14 A8 D10 B9 C10 A7 C9 A6 B8 C7 C8 A5 B7 D7 B6 C6 A4 B5 C5 A3 D5 C4 B4 B3 A2 C3 D8 D6 D4
Pin name VDD5 REQ# PRST# VSS VDD3 AD[29] GNT# AD[27] AD[30] VSS VDD5 AD[25] AD[31] AD[28] AD[26] AD[24] VDD3 VSS VDD5 AD[23] IDSEL AD[20] AD[22] AD[21] AD[16] VDD5 VSS VDD3
Attribute VDD5 PCI O PCI I VSS VDD3 PCI I/O PCI I PCI I/O PCI I/O VSS VDD5 PCI I/O PCI I/O PCI I/O PCI I/O PCI I/O VDD3 VSS VDD5 PCI I/O PCI I PCI I/O PCI I/O PCI I/O PCI I/O VDD5 VSS VDD3
C/BE[3]# PCI I/O
OVSNS 349
* : With a pull-up resistor VDD3 : A 3.3 V power-supply pin (for supplying I/O power and internal power) VDD5 : Either a 5 V power-supply pin or 3.3 V power-supply pin (for supplying power to PCI I/Os) OVSENSE : A power-sensing pin. Usually fixed to L. TEST0 to TEST3 : TEST pins. Use them in an open state. N.C. : Use this in an open state. VPDP : A TEST pin. Usually fixed to L. 7
MB86943B
s PIN DESCRIPTION
1. PCI Bus interface (89 pins))
Function class Pin name CLK System PRST# I 1 I/O I Number of pins 1 Description A pin for the PCI-bus clock input. The PCI-bus interface operates in synchronization with this clock, up to 33 MHz. A pin for the PCI system reset input. A signal for PCI system reset. This signal, when asserted, initializes everything within the companion chip. Pins for the address data signals. The 32 lower-order bits of PCI-bus address data. Pins for the command byte enable signals for the PCI-bus. In address phase, these pins indicate a PCI-bus command. In data phase, these pins indicate the effective byte lane of AD[31:00]. A pin for the PCI-bus parity signal. Indicates the even parity of AD[31:00] and C/BE[3:0]#, 36 signals in total. A pin for the frame signal. This signal indicates that the PCI bus cycle is being executed. This pin outputs the master (initiator) signal on the PCI bus. When the MB86943B is the initiator, this pin is used in output state. A pin for the initiator ready signal. Indicates that the PCI-bus master (initiator) is ready to complete a bus cycle. A pin for the target ready signal. Indicates that the accessed PCI target (resource) is ready to complete a bus cycle. A pin for the device select signal. Indicates that a PCI target decodes the address on the AD line to respond to a bus cycle. A pin for the stop signal. Indicates that the accessed PCI target is waiting for the bus cycle to finish before the PCI-bus master finishes access in whole or in part. A pin for the initialize device select signal input. The signal line AD[31:11] is used as the IDSEL signal line for each PCI resource. For this purpose, AD[31:11] are all used as an input pin for any resource. The signal lines AD[31:11] are driven by the PCI-bus master so as to select a specific PCI resource configuration space. A pin for the request signal output. A signal that conveys that the companion chip requests the PCIbus right. With the PRST# signal asserted, this pin is put to a tristate when involved in a point-to-point signal.
AD[31:00]
t/s I/O
32
Address data bus
C/BE[3:0]# t/s I/O
4
PAR
t/s I/O
1
FRAME#
s/t/s I/O
1
IRDY#
s/t/s I/O s/t/s I/O s/t/s I/O
1
Bus control
TRDY#
1
DEVSEL#
1
STOP#
s/t/s I/O
1
Bus control
IDSEL
I
1
Arbitration control
REQ#
t/s O
1
(Continued)
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MB86943B
(Continued) Function Pin name class
I/O
Number of pins
Description A pin for the grant signal input. A signal that notifies that the companion chip gained the PCI-bus from the PCI central arbiter in response to the request for the PCIbus right made by the companion chip. This is a point-to-point signal. A pin for the parity error signal. Indicates, in PCI-bus data phase, that a parity error occurred in data transferred on the signal lines - AD, C/BE#, PAR, and PAR64. When data are input to the companion chip, this pin is used for output. When data are output from the companion chip, this pin is used for input. A pin for the system error signal. Indicates, in PCI-bus address phase, that a parity error occurred in an address transferred on the signal lines - AD, C/BE#, PAR, and PAR64. When an error occurs that the companion chip can detect, the error can be notified as an SERR# by means of making suitable settings in the PCI SERR# Enable Register. A pin for the interrupt output. A pin that notifies the PCI-bus of an interrupt. When an error occurs that the companion chip can detect, the error can be notified as an INTA# by means of making suitable settings in the PCI-bus Interrupt Enable Register. Pins for the 64-bit expanded address data signals. The 32 higher-order bits of PCI-bus address data. Pins for the 64-bit expansion command byte enable signals. Pins for command byte enable signals for the PCI-bus. These pins are meaningless in address phase. In data phase, these pins indicate the effective byte lane of AD[63:32]. A pin for the 64-bit expansion PCI-bus parity signal. Indicates the even parity of AD[63:32] and C/BE[7:4]# 36 signals in total. A pin for the 64-bit data access request signal. Indicates that the PCI-bus master can execute a 64-bit data bus cycle. When a high-level signal is input to the SLD64 pin with the SPARClite bus being in 64-bit data operation and when the companion chip operates as the PCI bus master, the REQ64# signal is asserted concurrently with the FRAME# signal, and the 64-bit data cycles are always required. A pin for the 64-bit data access enable signal. Indicates that the accessed PCI target can execute a 64-bit data bus cycle.
Arbitration control
GNT#
I
1
PERR#
s/t/s I/O
1
Error notification SERR# o/d 1
Interrupt notification
INTA#
o/d
1
AD[63:32] t/s I/O
32
C/BE[7:4]# t/s I/O
4
PAR64 PCI 64-bit expansion
t/s I/O
1
REQ64#
s/t/s I/O
1
ACK64# Note : t/s s/t/s o/d pull up
s/t/s I/O
1
: Used as a tri-state output driver : Used as a sustained tri-state output driver : Used as an open drain output driver : Built-in pull-up resistance 9
MB86943B
2. SPARClite bus interface pins (138 pins)
Function class System clock Pin name CLKIN I/O I Number of pins 1 Description A pin for SPARClite bus clock input. The SPARClite bus interface operates in synchronization with this clock, up to 50 MHz. A pin for reset input from the SPARClite-bus. When the "L" level is input to this pin, the following operation is activated. (1) Clearing of the SL-bus Init Done bit of the SL-bus Configuration Register. (2) Clearing of the registers other than those related to the PCI Configuration. (3) Assertion of the SRSTO# signal. A pin for the reset output to the SPARClite-bus. This pin is asserted in one of the instances given below. (1) When the PRST# signal is input. (2) When the SRSTI# signal is input. (3) When "1" is set in the Software Reset bit of the Reset Register, which is related to the PCI Configuration. A pin for the PCI-bus host definition. A pin that decides whether or not the SPARClite should generate PCI configuration cycles as the host CPU of the PCI-bus. This pin is an input pin fixed either to the "L" level or to the "H" level. When the "H" level is being input to this pin: The SPARClite becomes the host CPU of the PCI-bus, and the companion chip is defined as a host bridge. In this instance, use of the SL-bus configuration related PCI Configuration Address Register and the PCI Configuration Address Register allows generation of configuration cycles into the PCI-bus. When the "L" level is being input to this pin: The PCI Configuration Address Register and the PCI Configuration Data Register, which are related to the SL-bus Configuration, are ignored when written and become indeterminate registers when read, so that configuration cycles cannot be generated into the PCI-bus. A pin for the SPARClite data bus width definition. A pin that decides the data bus width in the SPARClite-bus cycles in which the companion chip intervenes. This pin is an input pin fixed either to the "L" level or to the "H" level. When the "H" level is being input to this pin: The SPARClite-bus is defined as a 64-bit data width - D<63:0>, BE0# to BE7#, and PARITY0 to PARITY7 are regarded as valid. When the "L" level is being input to this pin: The SPARClite-bus is defined as a 32-bit data width - D<31:0>, BE4# to BE7#, and PARITY4 to PARITY7 are regarded as valid. D<63:32>, BE0# to BE3#, and PARITY0 to PARITY3 assume the state of high input impedance.
SRSTI#
I pull up
1
Reset
SRSTO#
t/s O
1
HOST
I pull up
1
Bus definition
SLD64
I pull up
1
(Continued)
10
MB86943B
Function class Pin name I/O Number of pins Description A pin for the SPARClite-bus burst transfer length definition. A pin that decides a burst transfer length in the SPARClite-bus cycles in which the companion chip intervenes. This pin is an input pin fixed either to the "L" level or to the "H" level. When the "H" level is being input to this pin: The SPARClite-bus, when subjected to a burst transfer, is defined as an 8-burst transfer. When the "L" level is being input to this pin: The SPARClite bus, when subjected to a burst transfer, is defined as a 4-burst transfer. A pin for the interrupt signal to the SPARClite. When a cause of interrupt specified by the SL-bus Interrupt Enable Register occurs, this pin is switched to the "L" level to notify the interrupt.
Bus definition
BST8
I pul up
1
Interrupt notification
IRQ#
O
1
(Continued)
11
MB86943B
Function class Pin name I/O Number of pins Description Pins for the address signal. When the companion chip has the bus right: This pin outputs an address signal. This pin is effective over a bus cycle period, and the output value during an idle cycle is not guaranteed. The value sequentially changes under a burst transfer. ADR<5:3> under burst transfer with a 64-bit bus width in operation changes as given below. [For 4-burst transfer] (1) 000001010011 (2) 100101110111 [For 8-burst transfer] 000001010011100101110111 ADR<4:2> under a burst transfer with a 32-bit bus width in operation changes as given below. [For 4-burst transfer] (1) 000001010011 (2) 100101110111 [For 8-burst transfer] 000001010011100101110111 When the companion chip doesn't have the bus right: This pin becomes an address input pin to be used to request the direct master access involved in internal registers. When SLD64 = "1" (a 64-bit data width specified) ADR<31:3> is regarded as a valid address in carrying out a single transfer. When a 4-burst transfer is in operation, the 2 lowerorder bits ADR<4:3> need to be 00, and when an 8-burst transfer is in operation, the 3 lower-order bits ADR<5:3> need to be 000. In other instances, a burst response called forth by the BMACK# signal is not made, but a single transfer is carried out. When SLD64 = "0" (a 32-bit data width specified) ADR<31:2> is regarded as a valid address in carrying out a single transfer. When a 4-burst transfer is in operation, the lower order 2 bits of address ADR<3:2> need to be 00, and when an 8burst transfer is in operation, the lower order 3 bits of address ADR<4:2> need to be 000. In other instances, a burst response called forth by the BMACK# signal is not made, but a single transfer is carried out.
Address bus
ADR<31:2>
I/O pull up
30
(Continued)
12
MB86943B
Function class Pin name I/O Number of pins Description Pins for the data signal. When the companion chip has the bus right: These pin form a bidirectional data bus. If data is of double-word type, the data needs to be aligned to an address of a multiple of 8, if data is of single-word type, the data needs to be aligned to a multiple of 4. D<31:0> is used in 32-bit burst mode. When the companion chip doesn't have the bus right: These pins form a data bus used to access internal registers, the external ECS space, and the PCI space from the SPARClite. Access by use of 64-bit bus width and access by use of 32-bit bus width are supported. Reading from the SPARClite is effected in conformity with a data size requested. In writing, valid bytes are specified by use of BE0# to BE7# for a 64-bit bus width, and by use of BE4# to BE7# for a 32-bit bus width. Specifying discontinuous BE#s is forbidden. Pins for the byte enable signal. When SLD64 = "1" (a 64-bit data width specified) The valid bytes enabled for D<63:0> are BE0# to BE7#. When SLD64 = "0" (a 32-bit data width specified) The valid byte enabled for D<31:0> are BE4# to BE7#. When the companion chip has the bus right: These pins output "L"s to valid bytes both in write and read. These signals are effective over a bus cycle. When the companion chip doesn't have the bus right: These pins are for a signal for specifying the valid byte data. In reading, any data of 64-bit width or 32-bit width are regarded as valid. In writing, data corresponding to active BEx#s are written. Discontinuous BEx#s are forbidden. Pins for the parity signals. These are data parity signals. When SLD64 = "1" (a 64-bit data width specified) The parity bits for D<63:0> are PARITY0 to PARITY7. When SLD64 = "0" (a 32-bit data width specified) The parity bits for D<31:0> are PARITY4 to PARITY7. When the companion chip has the bus right: When reading as viewed from the companion chip, these pins work as parity input; when writing, these pins work as parity output. When the companion chip doesn't have the bus right and accessed via the companion chip: When reading as viewed from the SPARClite, these pins work as parity output; when writing, these pins work as parity input.
Data bus
D<63:0>
I/O pull up
64
BE0# to BE7#
I/O pull up
8
Data bus information
PARITY0 to I/O PARITY7 pull up
8
(Continued)
13
MB86943B
Function class Pin name I/O Number of pins Description Pins for the address space identification input signal. When the companion chip has the bus right: These signals are meaningless. When the companion chip doesn't have the bus right: These pins are input pins for the address space identification signals output from the SPARClite. These pins pass input signals used for the SPARClite to intervene in the companion chip and to identify an address space. These pins are sampled at the cycle immediately subsequent to the cycle in which AS# is asserted. A pin for the windows input signal. When the companion chip has the bus right: This signal is meaningless. When the companion chip doesn't have the bus right: Some types of SPARClite CPUs do not support every bit of ADR<31:0>. Thus, in using one of SPARClites of such type, inputting the "L" level to this pin allows ADR<31:28> and ASI<3:0> not to be subjected to decoding. This pin is sampled at the cycle immediately subsequent to the cycle in which AS# is asserted. A pin for the register select input signal. When the companion chip has the bus right: This signal is meaningless. When the companion chip doesn't have the bus right: The "L" level signal input to this pin when the SPARClite accesses internal registers of the companion chip. This pin needs to be asserted during the relevant access cycle.
ASI<3:0>
I pull up
4
Address information
WINDOWS#
I pull up
1
RGSL#
I pull up
1
(Continued)
14
MB86943B
Function class Pin name I/O Number of pins Description A pin for the address strobe signal. When the companion chip has the bus right: An address strobe is output only when "1" is set in the SDRAM Mode bit of the SL-bus Configuration Register. An "L" is asserted for one clock cycle in the first cycle of the bus cycle. When the companion chip doesn't have the bus right: The address strobe is fed. A pin for the read/write signal. When the companion chip has the bus right: This is a read/write signal. An "L" is output if the current cycle is a write cycle; the "H" is output over the period of a read cycle. The output level is kept up from the beginning to the end of the bus cycle. When the companion chip doesn't have the bus right: This signal specifies the read/write when the SPARClite accesses internal registers, the PCI space, and the ECS space. This pin is sampled at the cycle immediately subsequent to the cycle in which AS# is asserted. And if it is "H", then read operation is carried out; if it is "L", then write operation is carried out. A pin for the burst transfer enable signal. When the companion chip has the bus right: A signal for a request for burst transfer toward the SPARClite. Either a direct slave or DMA access occurs only when "1" is set in the SDRAM Mode bit of the SL-bus Configuration Register. If the condition to carry out burst transfer is being satisfied, then make this signal "L" to request burst transfer. At the same time, the EBMREQ# signal is asserted, too. The EBMREQ# signal is deasserted at the same time with the first ready cycle. When the companion chip doesn't have the bus right: A signal for a request for burst transfer from the SPARClite. The level of this signal is determined at the cycle immediately subsequent to the cycle in which AS# is asserted. If it is "L" and if the timing permits burst transfer, then the burst transfer is performed in response to the BMACK#; if the timing doesn't permit burst transfer, then a BMACK# response is not made, and only a single transfer is carried out. In accessing an internal register or the ECS space from the SPARClite, the burst transfer is not responded even if a request for burst transfer is asserted.
AS#
I/O pull up
1
RDWR#
I/O pull up
1
Cycle control
BMREQ#
I/O pull up
1
(Continued)
15
MB86943B
Function class Pin name I/O Number of pins Description A pin for the burst transfer response signal. When the companion chip has the bus right: This signal is acknowledgment input from the SPARClite in burst mode. If the "L" level is input at the same cycle as READY# with burst transfer requested (with the "L" output to BMREQ#), the burst transfer mode is assumed. (This operation is feasible in both schemes - either the "L" is input in the same cycle as READY# or the "L" was input at a prior cycle and is kept until reaching the cycle of READY#.) When the companion chip doesn't have the bus right: In an instance in which the SPARClite decodes an address space accessed via the companion chip, this terminal outputs acknowledgment in burst mode. A pin for the burst transfer inhibit input signal. When the companion chip has the bus right: This signal is meaningless. When the companion chip doesn't have the bus right: An input pin for a signal to disable a burst transfer request. With the "L" input to this pin, the burst response with the BMACK# output is not performed even though a burst transfer is requested from the SPARClite. The level of this signal is determined at the cycle immediately subsequent to the cycle in which AS# is asserted; if it is "L", the BMACK# output is maintained at the "H" level. A pin for the ready signal output. When the companion chip has the bus right: If the companion chip has the bus right: This signal is output if a time-out occurs in the built-in ready timer. To make the ready timer effective, a longer time period needs to be set in the ready timer than the amount of wait given to the wait generator in each ECS space and than the setting in the external watchdog timer. When the companion chip doesn't have the bus right: In reading the internal register or the PCI space from the SPARClite, the "L" is output when data is made ready on the data bus. In writing to the internal register or to the PCI space, the "L" is output when data is taken into the companion chip. In accessing the ECS space from the SPARClite, a ready output signal internally generated comes out of this pin. This pin outputs a ready signal generated by the built-in wait generator. Also, it outputs this signal when a time-out occurs in the built-in ready timer. For this reason, to make the ready timer effective, a longer time period needs to be set in the ready timer than the amount of wait given to the wait generator and than the setting in the external watchdog timer.
BMACK#
I/O pull up
1
BMINH#
I pull up
1
Cycle control
READY#
t/s O pull up
1
(Continued)
16
MB86943B
Function class Pin name I/O Number of pins Description A pin for the ready signal input. This is a ready signal input when the companion chip has the bus right. This pin goes "L" when the data is made ready on the data bus in a read cycle or when the data is written in a write cycle. In carrying out burst transfer, ready signals need to be input a predetermined number of times with respect to a single-time assertion of AS# or EAS#. A pin for the SPARClite ready signal input. In using the wait generator of the SPARClite to access the ECS space from the SPARClite with no internal READY generated in the companion chip and with no READYIN# input from outside, connect RDYOUT# of the SPARClite to this pin. If the RDYOUT# output pin of the SPARClite has been connected to the READYIN# pin of the companion chip, no connection to this pin is required. In this instance, connect a pull-up resistor to this pin. A pin for the memory access exception signal output. A pin for outputting a memory access exception in a bus cycle of the SPARClite in which the companion chip intervenes. This signal is output together with the READY# signal when a time-out occurs in the built-in ready timer. A pin for the error notification signal input. An input pin for error notification signal from the SPARClite. When "1" is set in the SPARC_Error bit of the PCI-bus Interrupt Enable Register, an INTA# interrupt into the PCI-bus is asserted when the "L" level is input to this pin. This behavior has no effect on the companion chip's operation.
READYIN#
I pull up
1
RDYOUT# Cycle control
I pull up
1
MEXC#
t/s O pull up
1
ERROR#
I pull up
1
(Continued)
17
MB86943B
(Continued)
Function class Pin name I/O Number of pins Description A pin for the bus use right request signal output. A request signal for the bus use right passed from the companion chip to the SAPRClite. This signal is output when a SPARClite-bus request by means of DMA or a direct slave request occurs, or when the bus right is requested by a daisy-chain-connected device by means of the BRIN# signal input. The BREQ# signal is asserted when the BGRNT# signal is deasserted. A pin for the bus grant signal input. A signal enabling the bus right passed from the SPARClite to BREQ#. When the companion chip receives this signal, it either starts a transaction or outputs BGOUT# to a daisy-chain-connected device, and enables the bus right. Once BGRNT# is asserted to BREQ#, BGRNT# must not be deasserted until BREQ# is deasserted. If violated, the operation is not guaranteed. A pin for the bus-release request signal input. A pin for a bus-release request signal input from the SPARClite. If the "L" level is input to this pin while the companion chip retains the bus right, the bus-release request is canceled after the current cycle is completed or after the transfer on a cache line size basis is completed. A pin for the bus-use right request signal input. A pin for a bus-use request signal input from a daisy-chain-connected device. The "L" level input to this pin enables the BREQ# to request for the SAPRClite-bus. If the bus right is enabled by BGRNT# at this moment, this terminal outputs BGOUT# after a round robin arbitration within the companion chip, and enables a daisy-chain-connected device to use the bus right. The assertion of BRIN# needs to be effected at the time when the BGOUT# signal is deasserted. A pin for the bus-use right enabling signal output. A pin for a bus-use enabling signal output to a daisy-chain-connected device.
BREQ#
O
1
BGRNT#
I pull up
1
Bus right control PBREQ# I pull up 1
BRIN#
I pull up
1
BGOUT#
O
1
18
MB86943B
3. External ECS space control pins (6 pins)
Function class Pin name I/O Number of pins Description A pin for the address strobe signal output to the ECS space. When the companion chip has the bus right: This pin outputs an address strobe. The "L" is asserted for the first one clock cycle of the bus cycle. When the companion chip doesn't have the bus right: This signal is meaningless. Pins for outputting a chip select signal to pick the ECS space. When the companion chip has the bus right: Pins for outputting a chip select signal to pick the ECS space. This signal is effective over a bus cycle period, and is negated during an idle cycle. When the companion chip doesn't have the bus right: When the APARClite accesses the ECS space, these pins are used to output a chip select signal to pick the ECS space. This signal is effective over a bus cycle period started by EAS#, and is negated during an idle cycle. A pin for outputting a signal requesting burst transfer to the ECS space. When the companion chip has the bus right: A signal requesting the burst transfer to the ECS space. If either a direct slave or DMA access occurs and if the condition for burst transfer has been satisfied, this signal goes "L" and the burst transfer is requested. The deasserts this signal concurrently with the first ready cycle. When the companion chip doesn't have the bus right: This pin switches to "H" level output. A pin for inputting a signal responding to burst transfer from the ECS space. When the companion chip has the bus right: This signal is acknowledgment input from the ECS space in burst transfer mode. If the "L" level is input in the same cycle as READYIN# when the burst transfer is requested by EBMREQ# (with the "L" output to EBMREQ#), the switches to burst transfer mode. (This operation is feasible in both schemes - either the "L" is input in the same cycle as READYIN# or the "L" was input in a prior cycle and is kept until reaching the cycle of READYIN#.) When the companion chip doesn't have the bus right: This signal is meaningless.
EAS#
O
1
ECS[0:2]#
O
3
ECS space control EBMREQ# O 1
EBMACK#
I pull up
1
19
MB86943B
4. DMAC control pins (6 pins)
Function class Pin name I/O Number of pins Description Pins for DMA request signal input. A signal that requests the start of transfer when the built-in DMAC is started up in external startup mode. Since this signal is triggered at the "L" level, this signal needs to be kept asserted until the DACK0, 1# is encountered. Pins for DMA acknowledgment signal output. An acknowledgment signal indicating that the DREQ0, 1# is accepted. This signal is asserted concurrently with EAS#. Pins for DMA end signal output. A signal for the end of process. This signal indicates that transfer on a descriptor basis involved in DMA has been completed. This signal is asserted over a time period where the closing READYIN# is waited for to be input.
DREQ0#, DREQ1#
I pull up
2
DMA control
DACK0#, DACK1#
O
2
EOP0#, EOP1#
O
2
5. JTAG pins (5 pins)
Function class Pin name I/O I pull up I pull up I pull up I pull up O Number of pins 1 Description A pin for JTAG test data input. A pin for inputting data used in testing JTAG. Have this pin stay "H" level except when enabling the JTAG features. A pin for JTAG test mode input. A pin for inputting a mode setting used in testing JTAG. Have this pin stay "H" level except when enabling the JTAG features. A pin for JTAG test clock input. A pin for inputting a clock used in testing JTAG. Have this pin stay "H" level except when enabling the JTAG features. A pin for JTAG test reset input. A pin for inputting reset used in testing JTAG. Have this pin stay "H" level except when enabling the JTAG features. A pin for JTAG test data output. A pin for outputting data used in testing JTAG.
TDI
TMS
1
JTAG
TCLK
1
TRST#
1
TDO
1
6. TEST pins (4 pins)
Function class Pin name TEST0, TEST1, TEST2, TEST3 I/O Number of pins Description
TEST pins
O
4
Pins for test output. Leave them open.
20
MB86943B
s ABSOLUTE MAXIMUM RATINGS
(VSS = 0.0 V) Parameter Power supply voltage ( PCI I/O) Power supply voltage (SPARClite I/O, internal) Input voltage (PCI I/O) Input voltage (SPARClite I/O) Storage ambient temperature Overshoot Undershoot Symbol VDD5 VDD3 VI5 VI3 TSTG Rating Min. -0.5 -0.5 -0.5 -0.5 -55 Max. 6.0 4.0 VDD5 + 0.5 VDD3 + 0.5 125 Unit V V V V C
Within VDD + 0.1 V (Within 50 ns ) Within VSS - 0.1 V (Within 50 ns )
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
(VSS = 0.0 V) Parameter Power supply voltage (PCI I/O) VDD5 = 5 V VDD5 = 3.3 V Symbol VDD5 VDD3 VIL VIH5 VIH3 Ta Value Min. 4.75 3.15 3.15 -0.3 2.0 2.0 0 Typ. 5.0 3.3 3.3 25 Max. 5.25 3.45 3.45 0.8 VDD5 + 0.3 VDD3 + 0.3 70 Unit V V V V V V C
Power supply voltage (SPARClite I/O,internal) "L" level input voltage "H" level input voltage (PCI I/O) "H" level input voltage (SPARClite I/O,internal) Operating ambient temperature
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating conditionranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
21
MB86943B
s ELECTRIC CHARACTERISTICS
1. DC Characteristics
Parameter "L" level input voltage "H" level input voltage (PCI) "H" level input voltage "L" level output voltage "H" level output voltage (PCI) "H" level output voltage Input leakage current Trial state output leakage current Power supply current (VDD5) Power supply current (VDD3) Power consumption (VDD5 + VDD3) Pin capacity (PCI pin) Pin capacity (pins other than PCI pin) Symbol VIL VIH5 VIH3 VOL VOH5 VOH3 ILI ILZ IDD PD CPIN Conditions IOL = 2 mA IOH = -2 mA IOH = -2 mA VIN = 0 or VDD VOUT = 0 or VDD VDD5 = VDD3 = VI = 0, f = 1 MHz, 25 C (VSS = 0.0 V, Ta = 0 C to +70 C) Value Unit Typ. Max. TBD TBD TBD 0.8 VDD5 VDD3 0.4 VDD5 VDD3 5 5 TBD TBD TBD 18 16 V V V V V V A A mA mA W pF
Min. 0 2.0 2.0 0
VDD5 - 0.5 VDD3 - 0.5 -5 -5
2. AC Characteristics
Cautions for the measurement are as follows: * Each parameter, unless otherwise specified, is valid within the specified temperature range and power supply range. * Each voltage is measured with respect to the GND (VSS = 0 V) level. The reference point for measuring timing is 1.5 V, the input level is from 0.4 V through 2.4 V, the rise time and the fall time of incoming signal are not more than 1.5 V ns. * Do not short-circuit two or more output pins for one second or longer. * The external output capacitive load is 50 pF.
(1) SPARClite-IF All SPARClite interface AC characteristics are defined from the rising edge of the CLKIN signal. * Clock input (Ta = 0 C to +70 C) Value Parameter Pin name Unit Min. Max. CLKIN period CLKIN "H" time CLKIN "L" time CLKIN rise time CLKIN fall time CLKIN CLKIN CLKIN CLKIN CLKIN 20 8 8 CLK period x 3 2 2 ns ns ns ns ns
22
MB86943B
* Output (Ta = 0 C to +70 C) Parameter Data signal An address signal Parity signals A signal for byte enabling A signal for address strobe Read/write signal Bus use right request signal A signal for burst transfer request A signal for burst transfer response Ready signal output Output valid delay Output hold Output valid delay Output hold Output valid delay Output hold Output valid delay Output hold Output valid delay Output hold Output valid delay Output hold Output valid delay Output hold Output valid delay Output hold Output valid delay Output hold Output valid delay Output hold Pin name D<63:0> ADR<31:2> PARITY0 to PARITY7 BE0# to BE7# AS# RDWR# BREQ# BMREQ# BMACK# READY# MEXC# BGOUT# IRQ# SRSTO# Value Min. 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Max. 13 13 13 13 13 13 13 13 13 13 13 13 13 13 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Memory access exception Output valid delay signal output Output hold Bus use right enable signal An interrupt signal Bus reset output signal Output valid delay Output hold Output valid delay Output hold Output valid delay Output hold
23
MB86943B
* Input Parameter A signal for address space identification input An address signal Data signal Parity signal A signal for byte enabling A signal for address strobe A signal for burst transfer request A signal for burst transfer response Bus grant signal Bus-use right request signal Bus-release request signal Ready signal input SPARClite ready signal input A signal for register select input A signal for windows input A signal for burst transfer inhibit input Error notification signal Bus reset input signal Data bus width definition signal Bus host definition signal Bus burst transfer length signal Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Pin name ASI<3:0> ADR<31:2> D<63:0> PARITY0 to PARITY7 BE0# to BE7# AS# BMREQ# BMACK# BGRNT# BRIN# PBREQ# READYIN# RDYOUT# RGSL# WINDOWS# BMINH# ERROR# SRSTI#* SLD64 HOST BST8 (Ta = 0 C to +70 C) Value Unit Min. Max. 6 ns 2 6 ns 2 6 ns 2 6 ns 2 6 ns 2 6 ns 2 6 ns 2 6 ns 2 6 ns 2 6 ns 2 6 ns 2 6 ns 2 6 ns 2 6 ns 2 6 ns 2 6 ns 2 6 ns 2 Asynchronous ns Only the width specified Used by being tied to "H" or "L" Used by being tied to "H" or "L" Used by being tied to "H" or "L" Used by being tied to "H" or "L" Used by being tied to "H" or "L" Used by being tied to "H" or "L" ns ns ns
* : RESET input from SPARClite-bus (SRSTI#) requires at least 16 CLKIN cycles. 24
MB86943B
(2) External ECS Space Control Signals All AC characteristics of the signals given below are defined from the rising edge of the CLKIN signal. (Ta = 0 C to +70 C) Value Parameter Pin name Unit Min. Max. An address strobe signal Output valid delay to the ECS space Output hold A chip select signal to pick the ECS space Output valid delay Output hold EAS# ECS0# to ECS2# EBMREQ# EBMACK# 2 2 2 6 2 13 13 13 ns ns ns ns
A signal requesting burst Output valid delay transfer to the ECS Output hold A signal responding to burst transfer from the Input setup time Input hold time
(3) DMAC Control Signals All AC characteristics of the signals given below are defined from the rising edge of the CLKIN signal. (Ta = 0 C to +70 C) Value Parameter Pin name Unit Min. Max. DMA acknowledgment signal DMA end signal DMA request signal Output valid delay Output hold Output valid delay Output hold Input setup time Input hold time DACK0#, DACK1# EOP0#, EOP1# DRQ0#, DRQ1# 2 2 6 2 13 13 ns ns ns
(4) PCIbus-IF All PCIbus interface AC characteristics are defined from the rising edge of the CLKIN signal. * Clock input (Ta = 0 C to +70 C) Value Parameter CLKIN period CLKIN "H" time CLKIN "L" time CLKIN rise time CLKIN fall time Pin name Min. CLK CLK CLK CLK CLK 30 13 13 VDD5 = 3.3 V Max. CLKIN period x 3 2 2 Min. 30 13 13 VDD5 = 5 V Max. CLKIN period x 3 2 2 ns ns ns ns ns Unit
25
MB86943B
* Output (Ta = 0 C to +70 C) Value Parameter Output valid delay Output hold Output valid delay Output hold Output valid delay Output hold Output valid delay Output hold Output valid delay Output hold Output valid delay Output hold Output valid delay Output hold Output valid delay Output hold Output valid delay Output hold Output valid delay Output hold Output valid delay Output hold Output valid delay Output hold Pin name VDD5 = 3.3 V Min. Address data signal Command byte enable signal PCI bus parity signal Frame signal Initiator ready signal Target ready signal Stop signal Device select signal Request signal Parity error signal System error signal Interrupt notification signal AD[31:00] C/BE[3:0]# PAR FRAME# IRDY# TRDY# STOP# DEVSEL# REQ# PERR# SERR# INTA# 2 2 2 2 2 2 2 2 2 2 Max. 12 12 12 11 11 11 11 11 11 11 VDD5 = 5 V Min. 2 2 2 2 2 2 2 2 2 2 Max. 14 14 14 11 11 11 11 11 11 11 ns ns ns ns ns ns ns ns ns ns ns ns Unit
Asynchronous 1 CLK cycle at the minimum Asynchronous
26
MB86943B
* 64-bit expansion output (Ta = 0 C to +70 C) Value Parameter Output valid delay Output hold Pin name VDD5 = 3.3 V Min. 64-bit expanded address data signals AD[63:32] C/BE[7:4]# PAR64 REQ64# ACK64# 2 2 2 2 2 Max. 12 12 12 12 12 VDD5 = 5 V Min. 2 2 2 2 2 Max. 14 14 14 14 14 ns ns ns ns ns Unit
Output valid delay 64-bit expansion command byte enable signals Output hold 64-bit expansion PCI bus Output valid delay parity signal Output hold 64-bit data access request signal Output valid delay Output hold
64-bit data access enable Output valid delay signal Output hold
27
MB86943B
* Input (Ta = 0 C to +70 C) Parameter An address data signal Command byte enable signal PCI bus parity signal Frame signal Initiator ready signal Target ready signal Stop signal Device select signal Request signal Parity error signal System error signal Initialize device select signal PCI system reset signal Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Pin name AD[31:00] C/BE[3:0]# PAR FRAME# IRDY# TRDY# STOP# DEVSEL# REQ# PERR# SERR# IDSEL# PRST#* Value Min. 7 1 7 1 7 1 7 1 7 1 7 1 7 1 7 1 7 1 7 1 7 1 7 1 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Asynchronous Only the width specified
*: RESET input for PCI-bus (PRST#)requires at least 16 CLK cycles.
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MB86943B
* 64-bit expansion input (Ta = 0 C to +70 C) Parameter 64-bit expanded address data signals Input setup time Input hold time Pin name AD[63:32] C/BE[7:4]# PAR64 REQ64# ACK64# Value Min. 7 1 7 1 7 1 7 1 7 1 Max. Unit ns ns ns ns ns
64-bit expansion command Input setup time byte enable signals Input hold time 64-bit expansion PCI bus parity signal 64-bit data access request signal 64-bit data access enable signal (5) Other Signals Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time
(Ta = 0 C to +70 C) Pin name TEST0, TEST1, TEST2, TEST3 Value Min. Open Max. Unit
Parameter Test pin
29
MB86943B
s CAUTIONS AS TO BOARD WRITING
* In connecting the power source and GND, use multiple VDD and VSS pins. For the system board in which MB86943B is used, use a multi-layer board that includes the power (VDD) and GND (VSS) so as to supply stable power. Leave pins labeled "N.C." non-connected. * Insert a sufficient decoupling capacitor close to MB86943B. There is a possibility that the fluctuations in output level on a number of pins (especially those with a large capacitive load) among output pins of MB86943B have an effect that causes power supply to vary. * For a system that operates at a high frequency, a low-inductance capacitor and interconnection are recommended. The inductance can be decreased by means of making the distance between MB86943B and the decoupling capacitor short. * MB86943B requires two power supply systems - VDD5 (5 V or 3.3 V system) and VDD3 (3.3 V system). To power on or shut off them, follow the steps in sequence given below. To power on VDD3 VDD5 Signal To shut off Signal VDD5 VDD3
s ORDERINGINFORMATION
Part number MB86943BPB Package 352-pin Plastic BGA (BGA-352P-M03) Remarks
30
MB86943B
s PACKAGE DIMENSION
352-pin Plastic BGA (BGA-352P-M03)
35.000.20(1.380.008)SQ 32.500.10(1.280.004)SQ 2.300.20 (.091.008) 0.600.10 (.024.004)
31.750.20(1.250.008)
1.270.20 (.050.008)
0.15(.006)
INDEX
O0.750.15(O.030.006)
1PIN
C
1996 FUJITSU LIMITED BGA352004SC-1-1
Dimensions in mm (inches)
31
MB86943B
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8588, Japan Tel: +81-44-754-3763 Fax: +81-44-754-3329
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
http://www.fujitsu.co.jp/
North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, USA Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://www.fujitsu-fme.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220
http://www.fmap.com.sg/
F0002 (c) FUJITSU LIMITED Printed in Japan

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